seiko epson corporation 1 pf428-10 E0C6266 4-bit single chip microcomputer l core cpu architecture l 38.4khz/500khz twin clock operation l built-in, 2-ch. serial ports l svd circuit/2-ch. analog comparators n description the E0C6266 is an advanced single-chip cmos 4-bit microcomputer consisting of the e0c6200 cmos 4-bit core cpu. it also contains the rom, ram, 2-channel timer, event counter, start-stop serial ports, clock sync serial ports and 40 i/o ports. the E0C6266 provides an excellent solution for low-power consumption systems with clock functions. n features l cmos lsi 4-bit parallel processing l clock ..................................................... 38.4khz (typ.)/500khz (max.) (selectable by software) l instruction set ........................................ 108 instructions l instruction cycle time ............................ 130sec, 182sec or 312sec at 38khz (depending on instruction) 10sec, 14sec or 24sec at 500khz (depending on instruction) l rom capacity ....................................... 6,144 12 bits l ram capacity ........................................ 1,024 4 bits l input port ............................................... 12 bits l output port ............................................ 16 bits l i/o port .................................................. 12 bits l serial i/o port ........................................ 2 ports ? async; half-duplex, start-stop; transmission speed at 200, 300, 600, 1200, 2400 or 4800 bps; 6 to 8-bit data length; built-in error detect circuit and built-in send/receive buffer register. ? clock sync.; operating by external clock; start-stop can be set by mask option. l built-in time base counter, programmable timer, event counter, and watchdog timer l built-in svd circuit, 2 channels (internal voltage detection) l built-in comparator, 2 channels l built-in lcd drive power supply, double boosting, external adjustment of output voltage l interrupts ............................................... external : input interrupt 3 lines internal : timer interrupt 2 lines (4ch.) comparator interrupt 2 lines event counter interrupt 1 line serial i/o interrupt 2 lines l supply voltage ...................................... 2.2v to 5.5v l current consumption ............................ halt mode (38.4khz) : 1.8a (typ.) operating mode (500khz) : 110a (typ.)/150a (max.) l package ................................................ qfp6-60pin (plastic) die form wide voltage operation products
2 E0C6266 n block diagram ram 1,024 words x 4 bits serial port 1 serial port 2 power controller amp & svd interrupt generator input port test port i/o port output port time base counter programmable timer event counter k13 r00~03, r10~13, r20~23, r30~33 p00~03, p10~13, p20~23 k00~03, k10~13, k20~23 test v ca~ce v k10 p10~13 ss2 v ss v s1 v l1~4 v dd r32~33 k22~23 r30~31 k20~21 reset osc4 osc3 osc2 osc1 adj rom 6,144 words x 12 bits osc system reset control core cpu e0c6200
3 E0C6266 n pin configuration qfp6-60pin n pin description 31 45 16 30 index 15 1 60 46 E0C6266 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 p13 p20 p21 p22 p23 r00 r01 r02 r03 r10 r11 r12 r13 r20 r21 no. pin name 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ss2 r22 r23 r30 r31 r32 r33 k00 k01 k02 k03 k10 k11 k12 k13 no. pin name 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 k20 k21 k22 k23 reset test ce cd cc cb ca v l4 v l3 v l2 v adj no. pin name 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 v l1 v dd osc1 osc2 v s1 osc3 osc4 v ss p00 p01 p02 p03 p10 p11 p12 no. pin name v dd v ss v ss2 v s1 v l1 v l2 v l3 v l4 v adj ca?e osc1 osc2 osc3 osc4 reset k00?03 k10/v bld k11?12 k13/evn k20/si1a k21/si1b k22/si2 k23/sclk p00?03 p10/cmpp1 p11/cmpm1 p12/cmpp2 p13/cmpm2 p20?23 r00?03 r10, r11 r12/fout r13/bz r20?23 r30/so1a r31/so1b r32/so2 r33/srdy test pin name i i i i i o i o i i i i i i i i i i/o i/o i/o i/o i/o i/o o o o o o o o o o i in/out power source (+) terminal power source (-) terminal ...analog power source power source (-) terminal ...power source for output ports (r20?23) power source for oscillation circuit reduction power source for lcd power source for lcd booster power source for lcd booster power source for lcd input terminal for setting v l booster/reduction capacitor connecting terminals for lcd crystal oscillation input terminal crystal oscillation output terminal ceramic oscillation input terminal ceramic oscillation output terminal initial reset input terminal input terminal input terminal input terminal input terminal input terminal input terminal input terminal input terminal i/o terminal i/o terminal i/o terminal i/o terminal i/o terminal i/o terminal output terminal output terminal output terminal output terminal output terminal output terminal output terminal output terminal output terminal test input terminal (input terminal for setting svd detection voltage) (event counter input terminal) (serial port 1 data input terminal) (serial port 1 data input terminal) (serial port 2 data input terminal) (serial port 2 clock input terminal) (comparator 1 non-inverted input terminal) (comparator 1 inverted input terminal) (comparator 2 non-inverted input terminal) (comparator 2 inverted input terminal) (fout or bz output terminal) (bz or osc3 clock output terminal) (10 ma output available) (serial port 1 data output terminal) (serial port 1 data output terminal) (serial port 2 data output terminal) (serial port 2 status output terminal) 47 53 16 50 46 44 43 42 45 41?7 48 49 51 52 35 23?6 27 28?9 30 31 32 33 34 54?7 58 59 60 1 2? 6? 10, 11 12 13 14, 15, 17, 18 19 20 21 22 36 pin no. function
4 E0C6266 l recommended operating conditions condition supply voltage (1) supply voltage (2) * 1 oscillation frequency (1) oscillation frequency (2) * 2 capacitor between v dd and v s1 capacitor between v dd and v l1 * 3 capacitor between v dd and v l2 * 3 capacitor between v dd and v l3 * 3 capacitor between v dd and v l4 * 3 capacitor between ca and cb * 3 capacitor between ca and cc * 3 capacitor between cd and ce * 3 * 1: * 2: * 3: when selecting not to use v ss2 power by option, you can release the v ss2 terminal. when selecting not to use osc3 oscillation circuit by option, you can release the osc3 terminal. when selecting not to use lcd drive power by option, you can release the above capacitors are not required. however, you should connect v l1 ? l4 terminals with the v dd and release the ca?e and v adj terminals. symbol v ss v ss2 f osc1 f osc3 c s1 c l1 c l2 c l3 c l4 c1 c2 c3 remark v dd =0v v dd =0v duty: 50 5% unit v v khz khz f f f f f f f f (ta=-20 to 70 c) max. -2.2 v ss 500 typ. 38.400 min. -5.5 -5.5 50 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 l dc characteristics unit v v v v a a a a a a a a a ma (unless otherwise specified: v dd =0v, v ss (v ss2 )=-2.2 to -5.5v, ta=25 c) max. 0 0 0.8? ss 0.9? ss 0.5 -3 -3 -0.5 -300 -300 typ. min. 0.2? ss 0.1? ss v ss v ss -0.5 -20 -30 -20 -100 500 5 characteristic high level input voltage (1) high level input voltage (2) low level input voltage (1) low level input voltage (2) high level input current low level input current (1) low level input current (2) low level input current (3) low level input current (4) low level input current (5) high level output current (1) high level output current (2) low level output current (1) low level output current (2) symbol v ih1 v ih2 v il1 v il2 i ih i il1 i il2 i il3 i il4 i il5 i oh1 i oh2 i ol1 i ol2 v ih =v dd v il1 =v ss no pull up resistor v il2 =v ss with pull up resistor v il3 =v ss with pull up resistor v il4 =v ss v il5 =0.1? ss v oh1 =0.1? ss v oh2 =0.1? ss2 v ol1 =0.9? ss v ol2 =0.9? ss2 condition k00?3?0?3?0?3 p00?3?0?3?0?3 reset k00?3?0?3?0?3 p00?3?0?3?0?3 reset k00?3?0?3?0?3 p00?3?0?3?0?3 reset, test k00?3?0?3?0?3 p00?3?0?3?0?3 k00?3?0?3?0?3 p00?3?0?3?0?3 reset reset r00?3?0?3?0?3?0?3 p00?3?0?3?0?3 r20?3 r00?3?0?3?0?3?0?3 p00?3?0?3?0?3 r20?3 n electrical characteristics l absolute maximum ratings rating supply voltage (1) supply voltage (2) supply voltage (3) input voltage (1) input voltage (2) * 1 permissible total output current (1) * 2 permissible total output current (2) * 2 operating temperature storage temperature soldering temperature / time permissible dissipation * 3 * 1: * 2: * 3: osc1, osc2 pin the permissible total output current is the sum total of the current (average current) that simultaneously flows from the outpu t pins (or is draw in). in case of plastic package (qfp6-60pin). symbol v ss v ss2 v l1 ? l4 v i v iosc s i vss s i vss2 topr tstg tsol p d value -7.0 to 0.5 -7.0 to v ss -7.0 to 0.5 v ss - 0.3 to 0.3 -2.0 to 0.3 15 40 -20 to 70 -65 to 150 260 c, 10sec (lead section) 250 unit v v v v v ma ma c c mw (v dd =0v)
5 E0C6266 l analog circuit characteristics and current consumption * 1: * 2: * 3: * 4: * 5: when selecting not to use lcd drive power by option, v dd (=0v) is output to v l2 . the stabilizing time is the time from turning the circuit on until the output data stabilizes. the time base counter is run status, programmable timer, bld circuit and analog comparator are off status, and the input and output terminals are static status. the same status as * 1 and is when not using lcd drive power by option, and selecting dc output to the r12 port output form. the bld circuit and analog comparator are off status and the input and output terminals are static status. unit v v v v v v s a v mv s s a a a a a a (unless otherwise specified: v dd =0v, v ss =-2.2 to -5.5v, f osc1 =38.4khz(crystal), f osc3 =500khz(ceramic), ta=25 c, c g =10pf, c gc /c dc =108pf, v adj =v l2 , ra1/ra2=1m w , c s1 /c l1 ? l4 /c1?3=0.1 f) max. 0.45 v l2 -1.95 1.45 v l2 1.95 v l2 -2.20 -0.97 100 20 -1.0 50 100 100 10 15 4.0 3.0 15 150 typ. -2.10 -2.35 -1.05 10 4 8 1.8 1.3 9 110 min. 0.50 v l2 -2.25 1.50 v l2 2.00 v l2 -2.50 -1.13 v ss +0.3 characteristic lcd drive voltage * 1 bld voltage (internal) bld voltage (external) bld circuit stability time * 2 bld circuit current consumption analog comparator input voltage analog comparator offset voltage analog comparator stabilizing time * 2 analog comparator response time analog comparator current consumption (1) analog comparator current consumption (2) current consumption symbol v l1 v l2 v l3 v l4 v bld1 v bld2 t bld i bld v ip v im v of t cmp1 t cmp2 i cmp1 i cmp2 i op condition connect 1m w load resistor between v dd and v l1 (no panel load), v ss =-2.5 to -5.5v connect 1m w load resistor between v dd and v l2 (no panel load), v ss =-2.5 to -5.5v connect 1m w load resistor between v dd and v l3 (no panel load), v ss =-2.5 to -5.5v connect 1m w load resistor between v dd and v l4 (no panel load), v ss =-2.5 to -5.5v v ss =-3.0v noninverted input (cmpp) inverted input (cmpm) v ip =-1.0 to v ss +0.3v v im =-1.0 to v ss +0.3v v ip =-1.0 to v ss +0.3v v im =-1.0 to v ss +0.3v v ss =-2.2v v ip =-1.1v, v im =-1.1 0.1v v ss =-3.0v v ip =-1.4v, v im =-1.6v v ss =-3.0v v ip =-1.6v, v im =-1.4v during halt (1) * 3 during halt (2) * 4 during operation at 38.4khz * 3 during operation at 500khz * 5 oscc="0" no panel load no panel load unit sec pf ppm ppm ppm m w (unless otherwise specified: v dd =0v, v ss =-2.2 to -5.5v, crystal: c2-type(seiko epson), c g =25pf, c d =built-in, ta=25 c) max. 3 5 10 typ. 20 min. -10 40 200 characteristic oscillation start time built-in capacitance (drain) frequency/voltage deviation frequency/ic deviation frequency adjustment range permitted leak resistance symbol t sta c d ? f/ ? v ? f/ ? ic ? f/ ? c g r leak condition v ss =-2.2 to -5.5v for 60 pin plastic package v ss =-2.2 to -5.5v c g =5 to 25pf between osc1 and v dd , v s1 unit ms (unless otherwise specified: v dd =0v, v ss =-2.2 to -5.5v, ceramic: csb500e(murata mfg. co.), c gc =c dc =108pf, ta=25 c) max. 10 typ. 4 min. characteristic oscillation start time symbol t sta condition v ss =-2.2 to -5.5v l oscillation characteristics the oscillation characteristics change depending on the conditions (components used, board pattern, etc.). use the follow- ing characteristics as reference values. osc1 crystal oscillation circuit osc3 ceramic oscillation circuit
6 E0C6266 v osc1 osc2 v osc3 osc4 v dd s1 ss test reset v ss2 v v v v v ca cb cc cd ce l1 adj l2 l3 l4 E0C6266 c ssr c3 c2 c1 c l4 c l3 c l2 ra2 ra1 c l1 c 3.0v cd cr c s1 x'tal gx c gc c dc sr x'tal c gx cr c gc c dc c sr ra1, ra2 c l1 ~c l4 c1~c3 c s1 cd crystal oscillator trimmer capacitor ceramic oscillator 38.4khz 5~25pf 500khz 108pf 108pf 3.3 f 1m w 0.1 f 0.1 f 0.1 f 6.8 f n basic external connection diagram note: the above table is simply an example, and is not guaranteed to work. 14 0.2 17.6 0.4 31 45 14 0.2 17.6 0.4 16 30 index 0.35 0.1 15 1 60 46 2.7 0.1 0.1 3.1 max 1.8 0.85 0.2 0 10 0.15 0.05 0.8 n package dimensions plastic qfp6-60pin unit: mm
E0C6266 notice: no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko ep son. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is n o representation that this material is applicable to products requiring high level reliability, such as, medical products. moreover, no license to an y intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accord ance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade control law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ? seiko epson corporation 1999 all right reserved. seiko epson corporation electronic devices marketing division ic marketing & engineering group ed international marketing department i (europe & u.s.a.) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5812 fax : 042-587-5564 ed international marketing department ii (asia) 421-8, hino, hino-shi, tokyo 191-8501, japan phone : 042-587-5814 fax : 042-587-5110
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